Field of the Invention
The present disclosure relates to a display device, and more particularly, to a display device with improved display quality and a method of driving the same.
Discussion of the Related Art
Recently, as the information society progresses, display devices processing and displaying a large amount of information have rapidly advanced and various flat panel displays (FPDs) have been developed. For example, the FPDs may include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting diode (OLED) display devices and field emission display (FED) devices. Among various FPDs, an LCD device has been widely used due to its advantages such as small size, lightweight, thin profile and low power consumption.
In general, an LCD device receives a clock of a frequency of about 60 Hz from an external system and is driven according to the clock. Since the LCD device is driven with the clock having a frequency of about 60 Hz for an image such as a static image having a relatively small change in gray level between frames as well as an image such as a moving image having a relatively large change in gray level between frames, its power consumption increases.
To reduce the power consumption, a low refresh rate (LRR) driving method where the LCD device is driven with a clock having a frequency lower than about 60 Hz for an image having a relatively small change in gray level between frames has been suggested. Since a pixel maintains a pixel voltage for a longer time period, the LRR driving method may be effectively applied to a thin film transistor (TFT) using an oxide semiconductor material which has an excellent off current property.
FIG. 1A is a timing chart showing a gate voltage and a pixel voltage of an LCD device driven by a normal driving method according to the related art, and FIG. 1B is a timing chart showing a gate voltage and a pixel voltage of an LCD device driven by a low refresh rate driving method according to the related art.
Referring to FIG. 1A, when an LCD device is driven with a frequency of about 60 Hz, a gate voltage Vgn has a high level in each of first to sixtieth frames F1 to F60 constituting one second, and a data voltage is applied to a pixel of a display panel according to the gate voltage Vgn. To reduce or prevent accumulation of charges in a liquid crystal layer, the data voltages having opposite polarities are applied to the pixel by every two frames to be maintained as a pixel voltage Vpn for one frame.
In each of the first to sixtieth frames F1 to F60, as a result, the gate voltage Vgn has a high level during a normal charging period CPn such that a data voltage of a positive polarity (+) or a negative polarity (−) is alternately applied to the pixel, and the pixel voltage Vpn of a positive polarity (+) or a negative polarity (−) is maintained during a normal holding period HPn to display an image.
The normal charging period CPn corresponds to a time interval obtained by dividing about 16.7 msec of one frame by a number of pixels in a vertical pixel column, and the normal holding period HPn corresponds to a time interval obtained by subtracting the normal charging period CPn from about 16.7 msec of one frame. For example, in a full high definition (FHD) LCD device having a resolution of 1920×1080, the normal charging period CPn and the normal holding period HPn are about 15.5 μsec and about 16.68 msec, respectively.
Referring to FIG. 1B, when an LCD device is driven with a frequency of about 1 Hz, a gate voltage Vg1 has a high level in one of first to sixtieth frames F1 to F60 constituting one second, and a data voltage is applied to a pixel of a display panel according to the gate voltage Vg1. To reduce or prevent accumulation of charges in a liquid crystal layer, the data voltages having opposite polarities are applied to the pixel by every sixty frames to be maintained as a pixel voltage Vp1 for sixty frames.
In the first to sixtieth frames F1 to F60, as a result, the gate voltage Vg1 has a high level during a low refresh rate charging period CP1 such that a data voltage of a positive polarity (+) or a negative polarity (−) is alternately applied to the pixel, and the pixel voltage Vp1 of a positive polarity (+) or a negative polarity (−) is maintained during a low refresh rate holding period HP1 to display an image.
The low refresh rate charging period CP1 corresponds to a time interval obtained by dividing about 16.7 msec of one frame by a number of pixels in a vertical pixel column, and the low refresh rate holding period HP1 corresponds to a time interval obtained by subtracting the low refresh rate charging period CP1 from about 16.7 msec of one frame. For example, in a full high definition (FHD) LCD device having a resolution of 1920×1080, the low refresh rate charging period CP1 and the low refresh rate holding period HP1 are about 15.5 μsec and about 1 sec, respectively.
In the LCD device driven by the low refresh rate driving method, the pixel is charged up by the data voltage supplied once per one second corresponding to the sixty frames, and the pixel voltage Vp1 is maintained without an additional supply of the data voltage for most of one second corresponding to the sixty frames to display an image such as a static image having a relatively small change in gray level between frames. As a result, its power consumption can be reduced.
The LCD device driven by the low refresh rate driving method may have visual artifacts such as a flicker as compared with the LCD device driven by the normal driving method.
FIG. 2A is a timing chart showing a pixel voltage of an LCD device driven by a normal driving method according to the related art, and FIG. 2B is a timing chart showing a pixel voltage of an LCD device driven by a low refresh rate driving method according to the related art.
Referring to FIG. 2A, when an LCD device is driven with a frequency of about 60 Hz, a data voltage is applied to a pixel during a normal charging period CPn where a gate voltage Vgn has a high level, and the data voltage is maintained as a pixel voltage Vpn during a normal holding period HPn obtained by subtracting the normal charging period CPn from one frame. The pixel voltage Vpn is reduced by a normal voltage drop VDn due to a leakage current through the liquid crystal layer or the thin film transistor (TFT). As a result, the pixel voltage Vpn corresponding to an initial value of the data voltage is reduced by a normal voltage drop VDn due to the leakage current during the normal holding period HPn.
Referring to FIG. 2B, when an LCD device is driven with a frequency of about 1 Hz, a data voltage is applied to a pixel during a low refresh rate charging period CP1 where a gate voltage Vgn has a high level, and the data voltage is maintained as a pixel voltage Vp1 during a low refresh rate holding period HP1 obtained by subtracting the low refresh rate charging period CP1 from sixty frames. The pixel voltage Vp1 is reduced by a low refresh rate voltage drop VD1 due to a leakage current through the liquid crystal layer or the thin film transistor (TFT). As a result, the pixel voltage Vpn corresponding to an initial value of the data voltage is reduced by a low refresh rate voltage drop VD1 due to the leakage current during the low refresh rate holding period HP1.
Since the low refresh rate holding period HP1 is longer than the normal holding period HPn, an amount of leakage current during the low refresh rate holding period HP1 is greater than an amount of leakage current during the normal holding period HPn. As a result, the low refresh rate voltage drop VD1 is greater than the normal voltage drop VDn. (VD1>VDn)
The low refresh rate voltage drop VD1 may cause visual artifacts such as a flicker of an image displayed by the LCD device.
FIG. 3 is a view showing a pixel voltage and a luminance of an LCD device driven by a low refresh rate driving method according to the related art.
Referring to FIG. 3, when an LCD device is driven with a frequency of about 1 Hz, a data voltage is applied to a pixel during a low refresh rate charging period CP1, and a pixel voltage Vp1 is maintained without an application of the data voltage during a low refresh rate holding period HP1. An absolute value of the pixel voltage Vp1 at a beginning of the low refresh rate holding period HP1 right after the data voltage is applied is greater than an absolute value of the pixel voltage Vp1 at an end of the low refresh rate holding period HP1 right before the data voltage is applied due to a leakage current during the low refresh rate holding period HP1.
As a result, a luminance L1 of an image displayed by the LCD device sharply increases from a low value to a high value during a period A corresponding to the low refresh rate charging period CP1 and the beginning of the low refresh rate holding period HP1. The period A having the sharp increase in luminance L1 may have a time of about 20 msec due to a response speed of the liquid crystal layer. The sharp increase in luminance L1 during a relatively short time period can be recognized as a flicker, and the display quality of the LCD device may be reduced due to such a flicker.